I do not know much about this business. But I always assume that ECC is
an on-chip correction mechanism that allows localization of the error
bit. The traditional non-ECC does error checking by parity bit. So, one
byte is actually stored as 9 bits, with one parity bit. Normally, memory
chips are reasonably reliable. Occasional flip of one of the 8 data bits
would trigger the error signal on the bus logic which triggers re-read.
So, there is still a bit protection even without ECC. Of course, if two
of the 9 bits of the same byte get flipped, one has no way to know it.
This would give just wrong data. For ECC memory, one would have the same
problem when two bits flip at the same time, because ECC can really
correct just one bit of error.
Having said this, I must confess all my memory chips are ECC because
machine stability is a huge concern for me. I just do not like to spend
my or anybody's time to figure out what's wrong with the machines. Good
vendors tend to use ECC memory (and ask for higher price).
yong
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Received on Tue Oct 21 2003 - 03:53:01 PDT
